1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the testing of a design of a data processing circuit having a plurality of bus masters connecting via a shared bus to at least one bus slave.
2. Description of the Prior Art
As data processing circuits become more complex, this is reflected in the complexity of the bus system(s) that typically connect circuit elements. As an example, it is increasingly common to have multiple bus masters communicating with multiple bus slaves over a shared bus, which may be a multi-layer bus. When developing such designs, it is important that the designs should be thoroughly tested by way of emulation before the circuits are actually manufactured. Identifying problems during emulation is much more cost and time effective than first identifying those problems when the circuit has been physically built. In the context of the bus systems used within data processing circuits, one important aspect is to check that the bus itself is properly designed and connected to the various bus masters and slaves to permit the communication required. Another important aspect is that the various bus masters and bus slaves should be able to interact with each other and the bus in a manner whereby they can achieve the desired communication and performance whilst avoiding conflict with one another.
One approach to testing the design of bus systems is to provide separate emulations of a number of bus masters to be connected to the bus system and have those bus masters seek to drive the shared bus and communicate via the shared bus in accordance with their own scripts. This approach requires a disadvantageously large degree of engineering time and effort to undertake successfully and becomes increasingly difficult as the designs being emulated become more complex.